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Printed Circuit & Design Fab Circuits Assembly
December 2019
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December 2019 • VOL. 36 • NO. 12
First Person
6
Ceramic columns reveal brittle supply chain.
Mike Buetow
money matters
15
Youth will have its day – but not always its way.
Peter Bigelow
16
Invest in critical thinking skills.
Susan Mucha
18
Who should pay for tooling and test?
Greg Papandrew
Tech Talk
19
The relationship between epoxy resin and signal behavior.
Bill Hargin
21
Flex circuit solderability.
Mark Finstad
22
Handle with care.
Alun Morgan
42
On the road to screen printing utopia.
Clive Ashmore
43
Solder ball size variation.
Bob Willis
December 2019 • VOL. 36 • NO. 12
Features
23
PCB Design cover story
Good place and route technique can be complicated and painstaking. But it doesn’t always have to be time-consuming too.
by Brent Klingforth
29
Plating
Could a switch from standard immersion gold reduce plating defects?
by George Milad, Jon Bengston and Albin Gruenwald
34
iNEMI Roadmap
Development of interconnected digital technologies will enable electronics manufacturing companies to stay relevant.
by Daniel Gamota, Ph.D.
36
Productronica Recap
There was plenty of equipment to see at the biennial trade show, punctuated by advances in large-format process equipment, and AR/VR devices designed to enhance worker training and production.
by Mike Buetow
41
Retrospective
A look back at friends and colleagues who left us in 2019.
IN the Digital Edition
 
The latest happenings among the IPC Designers Council chapters.
by STEPHEN CHAVEZ

Departments

ON PCB CHAT (pcbchat.com)

 
Reliability Expectations of Automotive Electrical Systems
with Alun Morgan
 
The IPC Apex Expo Technical Conference
with Brook Sandy
 
All-Silicon Die Connection
with Puneet Gupta, Ph.D.
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Circuits Assembly CONTRIBUTING EDITORS AND ADVISORS
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Caveat Lector
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CCGAs Expose Brittle Supply Chain
F

PGAs are a multibillion-dollar business, characterized by suppliers like Xilinx, MicroChip, Texas Instruments and Cypress Semiconductor. So why are they reliant on a single source for copper-wrapped solder column attachment?

And not just any source. Six Sigma is a small, founder-run Silicon Valley-based company. For more than 30 years, it has performed a variety of third-party services, including solder dipping, BGA reballing, and solderability testing. It also happens to be the sole supplier of copper-wrapped solder column attachment services to the major FPGA vendors. And according to industry watchers, that leaves the supply chain in something of a pickle.

The risk with any sole source is something happens that affects their ability to make deliveries. Such an outcome would spell disaster for the high-rel companies that use column grid arrays (CGAs). And loss of access to the unique copper-wrapped columns used in key programs, including military and space, would put those applications at severe risk.

One alternative is organic packages. An investigation published by Reza Ghaffarian at Jet Propulsion Laboratory in 2006 found solder joint reliability of plastic BGA packages on polymeric boards to be generally superior to that of the ceramic versions due to the CTE mismatch between the ceramic balls and the substrate. In 2015, new work performed by Martin Hart of TopLine found solder columns on ceramic packages to be more compliant than solder balls, and able to absorb CTE mismatch of up to 10ppm/oC when soldered on a PCB.

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Around the World
PCD&F People
APCT named Bill Schwerter director of strategic sourcing.
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Bürkle North America appointed Kurt Palmer president and CEO. Palmer has over 30 years of experience in consumable and equipment distribution throughout North America. He previously served as vice president of sales for Bürkle North America, director of operations for TCT Circuit Supply, and co-owner of Tapco Circuit Supply.
Jamie Crichton Image
Isola named interim CEO Travis Kelly president and chief executive. He comes to the laminate supplier from an affiliate of Cerberus Capital Management, the private equity firm that owns Isola.
Jamie Crichton Image
National Instruments promoted current president and COO Eric Starkloff (pictured) to president and CEO, effective Feb. 1. He replaces Alex Davern , who was CEO for three years.
Shennan Circuits USA named Luis Rivera regional FAE manager.
Summit Interconnect named Marc Strickland flex operations manager.
PCD&F Briefs

Advanced Circuits completed its previously announced move to a new 50,000 sq. ft. location in suburban Phoenix and invested $4 million in new equipment at the site.

Apple reportedly is testing a smartphone with a wraparound display, one that makes use of the sides and rear of the handset.

Chemnitz University of Technology and Fraunhofer researchers have developed a combination of inkjet and screen printing, called multi-material 3-D printing tools, and are using it to develop electronic 3-D printed objects.

Around the World
Ucamco to Add Assembly to Gerber X3 Format

GENT, BELGIUM – Ucamco in November announced plans to extend its Gerber data transfer format to include components. The company is seeking comments on the proposed new specification, which adds component layers to the top and bottom of the Gerber file structure.The new layers show component location, shape, fiducial locations and footprints, all data that fit with the Gerber format’s image files. These data are supported by a new set of attributes specific to the component layers and that provide non-geometric information about the component such as manufacturer part numbers.

The new layers are described using Gerber’s existing syntax and methodology, added the company in a statement.

The development would bring Gerber closer in line with competitive formats such as IPC-2581 and ODB++, which for years have incorporated assembly attributes.

In a press release, Ucamco managing director Karel Tavernier said, “While designs for bare boards are transferred using Gerber files, the associated component data are typically contained in separate, non-standardized drawings and pick-and-place and BoM files. The Gerber format lends itself perfectly to the transfer of component data, as well as bare board data, and so it is a natural step for the format to be used to describe the board in its entirety.”

Around the World
PCB West 2020 Show Floor Selling Out

ATLANTAThe exhibition floor space for PCB West 2020 is more than 80% sold as of Nov. 5, UP Media Group said. Booth sales began the first week of October, and the show floor is expected to sell out for the ninth year in a row, show organizers added.

“We sold 70% of the booths in the first 48 hours show renewals were available, and we fully expect to sell out the show floor again for 2020,” said Frances Stewart, vice president of sales and marketing, UP Media Group. “While the early bird discount deadline has passed, we continue to get renewals and interest from new vendors because of the strong attendance and value for the money.”

PCB West will be held Sept. 8 – 11, 2020, in Santa Clara, CA. The event includes a four-day technical conference and one-day exhibition to be held at the Santa Clara (CA) Convention Center.

PCB West provides a conference and exhibition focused on the design and manufacture of PCBs, HDI, electronics assembly and circuit board test. The September 2019 event attracted more than 2,400 registrants.

PCB West 2020
Conference: September 8 – 11
Exhibition: Wednesday, September 9
Network with peers, colleagues and experts. Connect with fabricators, assemblers and engineers from around the world. It’s the place to be in the Silicon Valley.
Get real, practical, in-depth training and information from leading industry experts. Improve your skills, increase your knowledge and learn from the best.
See the latest innovations from the electronics supply chain at our free exhibition. Check out over 100 exhibitors displaying the latest software, services and products.
See you next year…
PCbwest.com
SANTA CLARA CONVENTION CENTER, CA
Around the World
Samsung Develops First 12-Layer 3D-TSV Chip Packaging Technology
SEOUL – Samsung Electronics in October announced it has developed the industry’s first 12-layer 3D-TSV (through-silicon via) technology. The innovation, which is used for mass production of high-performance chips, requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.
Cross-section of the 8- and 12-layer TSV package.
NICE PACKAGE Cross-section of the 8- and 12-layer TSV package.

The thickness of the package (720µm) remains the same as current 8-layer high bandwidth memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity, without having to change their system configuration designs.

Around the World
CA People
Cogiscan promoted Greg Benoit to director of business development.
Mycronic promoted Jeff Leal to head of product management.
Neways appointed Eric Stodel CEO. In his 30-year career, he has held various leadership roles and senior management positions at Flextronics, Solectron, Driessen, B/E Aerospace, and Marinoffs.
Sanmina named Kurt Adzema EVP and CFO. He most recently served as CFO at Finisar.
Screaming Circuits promoted Duane Benson to director of marketing.
Valtronic announced Sunita Kembhavi as purchasing manager and Brett Crane as production manager.
VJ Technologies named Lian Li general manager in China. She has a bachelor’s degree in mechanical technology and equipment, and was an engineer at ScienScope and vice general manager at Unicomp.
Around the World
Researchers Report a New Way to Produce Curvy Electronics
HOUSTON Contact lenses that can monitor your health, as well as correct your eyesight, aren’t science fiction, but an efficient manufacturing method – finding a way to produce the curved lenses with embedded electronics – has remained elusive.

Until now. A team of researchers from the University of Houston and the University of Colorado Boulder reported developing a new manufacturing method, known as conformal additive stamp printing, or CAS printing, to produce the lenses, solar cells and other three-dimensional curvy electronics. The work, reported in the journal Nature Electronics, demonstrates the use of the manufacturing technique to produce many curvy devices not suited to current production methods. The work is also highlighted by the journal Nature.

“We tested a number of existing techniques to see if they were appropriate for manufacturing curvy electronics,” said Cunjiang Yu, Bill D. Cook Associate Professor of Mechanical Engineering at the University of Houston and corresponding author on the paper. “The answer is no. They all had limitations and problems.”

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Around the World
CA Briefs

BESTProto installed a Mycronic MY-600 solder paste printer.

Cal-Comp Technology (Philippines) has decided for the second time to withdraw its planned $210 million IPO on the local exchange.

Celestica is cutting ties with Cisco, its largest customer at $750 million annually, after failing to meet profitability targets.

Cornell Capital announced an investment in Lorom Holding , a provider of cable and printed circuit assembly.

Critical Manufacturing has partnered with Cogiscan to deliver advanced smart factory solutions for electronics manufacturers.

Fabrinet has signed a lease for a building in Israel, where the EMS firm plans to establish an NPI assembly facility.

Kongsberg Defence & Aerospace placed an order with Kitron worth about $10 million.

Lightspeed Manufacturing has moved to a larger EMS facility in Haverhill, MA, to accommodate growth.

Neo Tech expanded its partnership with electronic thermostat OEM Pro1 .

Optomec has delivered its 500th industrial 3-D printer, this one to a division of General Electric.

Out of the Box Manufacturing purchased a Kurtz Ersa HR 600/2 Hybrid rework system.

Pegatron will not rule out setting up new factory sites in Vietnam and India to satisfy customer demand, according to company president and CEO SJ Liao.

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Market Watch
IPC: 90% of US Electronics Manufacturers ‘Troubled’ by Higher Tariffs
EDITED BY CHELSEY DRYSDALE
BANNOCKBURN, ILAlmost 90% of US electronics manufacturers are troubled by the higher tariffs imposed by the US and China on each other’s imports, and some are investing less in the US and hiring fewer workers as a result, according to new IPC survey results.

On average, companies report tariff increases on 31% of the total dollar value of the products they import. Twenty-five percent of companies report over half of the dollar value of the products they import are facing higher tariffs.

IPC queried its US members between Sept. 25 and Oct. 2.

Some 69% of companies report lower profit margins as a result of increased tariffs, with a ripple effect of negative consequences: 21% report they are reducing investment in the US, and 13% say they are cutting back on hiring and/or reducing headcount.

More than a third of companies report they cannot increase their prices to cover the cost of higher import tariffs because of various factors.

ROI
Speed Freeze
As veteran engineers know, sometimes less is more, and a lot faster.
Our industry is noted for spectacular new technology that eclipses everything around it at breathtaking speed. As exciting and noteworthy as those technologies may seem, however, success more often moves in ways and at speeds akin to the proverbial turtle. Patience pays.

The virtue of patience struck me while attending a regional industry event. The afternoon included technical presentations and a tour of an advanced manufacturing facility. The tour was conducted by energetic, sharp, intelligent young engineers who were excited and proud to show off the fruits of their labors. The facility did not have the latest equipment, but these innovative young bucks set up the equipment to take full advantage of the latest in holistic ergonomic advances, lean material logistics, and had a connected digital ecosystem that would make any Industry 4.0 proponent proud.

The tour was topped off by a strategic Star Wars-inspired planning room where stakeholders from all over the company connect via a real-time, 360° media area to look at problems, products, opportunities, and perform the necessary planning to ensure the highest level of quality in the quickest turn time. This collaborative media war room was designed to maximize communication to expedite decision-making. Someone asked how much time this protocol saved. Perhaps the vague reply should have been a warning: “Our productivity has increased significantly by having all stakeholders actively involved … .”

Focus on business
Preparing for the Workplace of Tomorrow
Workers need to understand the “why” of manufacturing and how to manage processes.
The pace of technological change continues to increase. Products are getting smaller and more challenging to build. The increased levels of automation needed to build those products are driving a need to rethink the role of the personnel associated with those machines. The worker who fills those new jobs needs to understand the “why” of manufacturing and have the critical thinking skills to manage processes rather than just run machines.

One example of this role rethinking is happening at Burton Industries, an electronics manufacturing services (EMS) provider whose primary manufacturing facility is in Michigan’s Upper Peninsula.

“We believe it is our responsibility to stay in front of the technology needs and expectations of our customers,” said Gary Burnett, president and CEO, Burton Industries. “While we’ve made the investment in the equipment needed to support advanced manufacturing challenges, we also see the need to create an internal culture where every employee recognizes the very important role they play in helping our customers succeed. To that end, we have moved away from the traditional model of machine operators and inspectors supported by engineering and quality assurance managers in our surface mount device (SMD) area. Our model now requires all SMD area team members to obtain and possess skill level and training equal to process engineers. Each team member now has a training plan designed to accomplish that. To incentivize that extra effort, we’ve made these positions some of the highest-paid in our facility.”

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Board Buying
Should PCB Buyers Pay Tooling and Testing Charges?
Automation and faster amortization should mean lower costs.
PCB manufacturers often include nonrecurring engineering (NRE) and electrical test (ET) charges in quotes, in addition to the piece price. During my training sessions for board buyers, I am frequently asked how to avoid those charges.

It’s a good question.

When I started in this industry some – ahem – 30 years ago, NRE charges were approximately $100 per conductive layer, meaning a 4-layer PCB was $400; a 6-layer PCB was $600, and so on. Back then, it took a lot of labor hours to create manufacturing files from a piece of original artwork, as nothing was as digital as it is today.

With advances in technology, releasing an order to the manufacturing floor requires a fraction of the time it once did. Sure, some board manufacturers still do some things manually, but most have adapted their front-end engineering to incorporate technological advances.

MATERIAL MATTERS
What Surrounds a Typical Trace?
At higher speeds, the micro-environment around traces can alter simulation results.
In the past few weeks, e-mails from multiple sources crossed my inbox asking about the relationship between epoxy resin and signal behavior. With a couple of SI guys on one side and a career PCB manufacturing guy on the other side hitting me the same week with different versions of the same question, I thought it would make for an interesting column topic.
Figure 1 shows the initial image I was provided, along with the question what surrounds a typical trace? At face value, this may sound trivial, but it’s a reasonable issue for a signal-integrity practitioner to be concerned about.

The answer depends on what’s above the signal layer, what’s below it, and where it appears in the stackup. Figure 1 is a reasonable representation of an inner stripline layer, if the cross-hatched dielectric representation is a prepreg with a fully cured core above it. In this case, the copper features on the signal layer are encompassed by a layer of resin that comes from the adjacent prepreg, as a result of heat and pressure applied during the lamination process.

Representative of a stripline
Figure 1. This started as a microstrip representation, but it’s more representative of a stripline.
THE Flexperts
Why ‘Born on Dating’ is Not a Reliable Means for PCB Shelf Life
Flex circuit solderability and life expectancy are influenced by handling and finishes.
What is the shelf life of a flex circuit if it stays in its original sealed packaging? And what is the life expectancy of a flexible circuit?

I assume the first question refers to long-term solderability and the second to the overall functionality of the flex circuit once installed in the final application.

As far as long-term functionality goes, flexible circuits in a static application really don’t have a post-installation “best if used by” date. There are flexible circuits over 25 years old still functioning without issue in military and avionics systems. Flexible circuits have also been used for decades in satellite applications due to their very low mass and high connection density. Considering the cost of a service call to a satellite, only the most reliable interconnects are used in these applications. That flexible circuits are still in use after all these years is a testament to their long-term reliability. The only exceptions to overall life expectancy are flexible circuits operating in very harsh environments, such as continuous temperatures above 275°F, strong acid or caustic exposure, abrasion, etc.

Material Gains
Materials Supply Chain Security
Between counterfeits and improper handling, the potential for consequences is rampant.
I’m a huge fan of the connected world. I’ve commented previously on the many potential benefits for communities everywhere. Like many good things, however, it poses its own set of challenges. One of these is the “democratization” of cyber-crime. The spread of the IoT means we are all vulnerable in our connected homes, our connected cars, or when enjoying the efficiencies of connected infrastructures and smart services. The potential consequences of cyber-attacks are no longer an issue only for banks, governments or large corporations. The consequences of a hacked car or medical device can be personal, real-time, and in some instances life-threatening.

IoT software protocols and hardware-device security down to the silicon level are being developed to counter a host of potential attacks that can range from stealing stored passwords or intellectual property to taking over devices and systems using malicious firmware. This will be an ongoing battle of “arms versus armor.” Other potential security threats such as counterfeiting are more mature, less fast-paced, but costly and potentially dangerous. Counterfeit electronic components are reckoned to cost the industry billions of dollars every year, although the Semiconductor Industry Association points out that the safety implications and potential threat to life posed by rogue components often worth only a few cents each make this a far more serious issue than financially larger black markets such as those for counterfeit high-value luxury goods.

The Route
Closing Out 2019 on a Positive Note
Local chapter events, plus a great keynote in North Carolina.
Wow! I can’t believe it’s December already. The IPC Designers Council chapters had another active year filled with great industry content from various industry events and chapter activities. From chapters that remain very strong to an old legacy chapter being resurrected and a new chapter formed, local entities continue to be active in their respective regions. We finish our 2019 chapter update series by highlighting the Silicon Valley Chapter and the Research Triangle Park (RTP) Chapter, plus some comments on the Designer Certification program.
Silicon Valley Chapter
Chapter leader: Bob McCreight
The Silicon Valley Chapter held its final 2019 meeting Oct. 24 in Milpitas, CA. Thanks to Sierra Circuits for recording the meeting and their complementary slides. Much appreciation goes out to Footprintku and Zuken for their roles in hosting and sponsoring the meeting. The combined team did a great job, and we look forward to working with them again for next year’s fourth quarter meeting. We had 35 attendees. The venue was excellent, and the lunch was enjoyable. The topic, presented by Scott Nance, was informative and contained a lot of great PCB design material. I would also like to give a shout-out to Optimum Design Associates for its involvement. The next chapter meeting will be Feb. 13. More details will come in early 2020.
PCB Design
Layout Automation Using Advanced PCB Design Techniques
Good PCB design doesn’t have to be time-consuming. by BRENT KLINGFORTH
After 25-plus years of PCB design, I could not imagine going back to designing a PCB as I did in the late ’90s or even early 2000s. New technology is constantly added to tools to simplify our job. The key is staying abreast of these technologies. If you are not using advanced techniques like high-speed routing and tuning, placement planning groups, design reuse, plane generation automation and others, your design completion time could be delayed up to 70% or more.

Most designers start a PCB design by grouping parts using cross-probing from the schematic. However, using a spreadsheet-based view (Figure 1) allows us to quickly see information about components and groups created for each circuit. These groups can be created either in the schematic or PCB layout.

Today, every design contains some sort of I/O interconnect, visual indicators and mounting features that need to interact with a mechanical enclosure. In most cases, the mechanical engineer will define the locations of these objects and even place 3-D models to support their design efforts.

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Plating
Elimination of Ni Corrosion in ENIG and ENEPIG by Using Reduction Assisted Immersion Gold
Could a switch from standard immersion gold reduce plating defects? by GEORGE MILAD, JON BENGSTON AND ALBIN GRUENWALD
Ed.: This article is adapted from a paper from the SMTA International Proceedings and is published with permission of the authors.
Nickel corrosion in electroless nickel immersion gold (ENIG) and electroless nickel electroless palladium immersion gold (ENEPIG) is occasionally reported, when encountered at assembly, manifested as soldering failures in ENIG and wire-bond lifting in ENEPIG. Although this is not common, when encountered it is very disruptive. Its presence can cause delays, missed delivery schedules, supply-chain disruption, failure analysis investigations, and manufacturer liability.

To highlight and mitigate nickel corrosion defects, the IPC Plating Processes Subcommittee revised the 2002 standard IPC-4552, Performance Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards. That revision, IPC-4552A, was released in 2017. Work on revision B took place in 2019, and that document awaits a final IPC member vote. Upon release of IPC-4552B, corrosion inspection will become mandatory.

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inemi roadmap
Digital Building Blocks
AI and machine learning will shape the coming era of electronics manufacturing. by DANIEL GAMOTA, PH.D.
Ed.: This is the third of an occasional series by the authors of the 2019 iNEMI Roadmap. This information is excerpted from the Smart Manufacturing chapter of the roadmap, available from iNEMI (inemi.org/2019-roadmap-overview).
Smart manufacturing is considered a “journey” that will require hyper-focus to ensure the appropriate technology foundation is established. Several enabling “horizontal” technologies (digital building blocks, data flow, security) are considered the most important to build a strong, agile, and scalable foundation. This article presents digital building blocks, with a focus on artificial intelligence (AI) and machine learning (ML) tools, and digital twins.

Advancements in the development of digital building blocks (interconnected digital technologies) are providing digitization, integration and automation opportunities to realize smart manufacturing benefits. These building blocks will enable electronics manufacturing companies to stay relevant as the era of the digitally connected smart infrastructure is developed and deployed.

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Productronica RecAP
Bigger is Better at Productronica
Bigger is Better at Productronica
The biennial trade show was busy and upbeat, suggesting good times are still ahead. by Mike Buetow

Four years after making their Productronica debut, there were scores of AVGs and AVIs, but oddly no one at the biennial trade show was talking about them. Benchtop robots were everywhere too, to little fanfare.

What was hot, however, was process machines built for large-format boards, which are increasingly seen due to the 5G rollout and LED ramps, and virtual reality/augmented reality devices designed to enhance worker training and even production. And sensors are in everything.

The trek to Munich revealed a remarkably upbeat mood, especially in light of Brexit, widespread political upheaval, and US trade wars. While traffic seemed lighter than the recent past, Productronica remains the largest trade show by far for the PCB fabrication and assembly equipment markets outside Asia. Show organizers touted 44,000 attendees, a figure that at times seemed almost believable.

RETROSPECTIVE
In Memoriam
A look back at friends and colleagues who left us in 2019.
Joseph Boyd, 98, CEO, Harris Corp.

Gary Burrell, 81, cofounder, Garmin.

Dominick Frank Canace, 87, electromechanical and PCB printed circuit designer with several companies including Tyco Electronics.

Andrew Chase, 55, president and CEO, Sunburst EMS.

Celia Mora Cuadra, 89, PCB assembler, Regitel, Grangers and Lipton Industries.

Carolyn (Puskas) Davis, 76, ex supervisor, Printed Circuit.

Darrell J. Lowrance, 80, founder, Lowrance Electronics; developed the first graph recorder and first integrated sonar/GPS unit.

Ed McBain, packaging engineer with Zilog, Harris, Promex and others.

Ralph Morrison, 91, PCD&F contributor and author of more than 12 books on currents and voltage in PCBs.

Michael Mügge, 56, sales engineer, Viscom.

Laurence “Larry” Murphy Jr., 82, salesperson, Alco Electronics.

Screen Printing
Dog Ears and Witch Hats
Achieving printing nirvana is largely dependent on solder paste material, print speed and deposit release.

Ahhhhh … screen printing utopia. We process engineers strive for this existence. In a perfect process, printed solder paste would emerge from the stencil as exact replicas of the aperture shape: nice, flat, brick-like deposits. And, while modern printers and advanced materials get us close, solder paste is still, well, solder paste. The materials are not inks; they have a grain structure that is getting smaller in size and distribution and is suspended in flux. Try as we might, with these particles, there will be material undulation at best, and flat paste surfaces will likely never be a certainty.

With printing, we must be pragmatic. It’s not a digital process, and many variables come into play. The goal, of course, is to fill all the apertures on the stencil fully with solder paste to obtain the best deposit shape and volume possible. This is easier said than done, as the range of aperture sizes across a stencil can be broad, with 1mm square, 300µm and 200µm openings next to one another. Each of those apertures – from the very large to the very small – must be filled. Since printing with different thickness stencils is a nonstarter (generally and practically speaking), compromise is required, and that challenges our utopian ideal. Squeegee pressure, stencil thickness, print speed and separation speed must be balanced to accommodate variations in required deposit sizes. When all inputs aren’t optimized and in perfect balance, solder deposit shape differences can have the potential to introduce process problems. Known in the printing world as “dog ears” on square or rectangular deposits and “witch hats” on circular deposits (Figure 1), these solder paste deposit peaks may be defect bugbears, especially in the world of high-density, miniaturized assemblies.

Defect of the Month
What Solder Ball Size Variation Can Tell Us
Measuring BGA joints can reveal process problems.

This month we show variation in the size of the solder joints on a section of a BGA. Measuring variation on solder ball size after reflow is useful. Even better is when measurements are taken automatically with an x-ray system, as this provides a good comparison tool between NPI and production builds.

Measuring NPI build, and saving the measurement data, provides a good point of reference when problems are seen on a build. It is also useful when moving between contractors or in the event of changes due to other process modifications.

Figure 1. is an x-ray image of the corner of a soldered BGA. There is variation in joint size from the device edge to the package center. Variation in ball size most likely indicates warping of the device in the center of the package or at the edges.

We have presented live process defect clinics at exhibitions all over the world. Many of our Defect of the Month videos are available online at youtube.com/user/mrbobwillis.

An x-ray of the corner of a soldered BGA
Figure 1. This x-ray of the corner of a soldered BGA indicates possible device warping.
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Technical Abstracts
In Case You Missed It
High-Density Connectors

“Qualification of High-Density Connector Solutions for Military and Avionic Environments”

Authors: Kim Cho, Tim Pearson, David Hillman and Ross Wilcox; kimera.cho@collins.com.

Abstract: This paper discusses the qualification of high-density connector solutions for rugged military and avionics environments. As electronic products have become progressively smaller in size, there has been a corresponding increase in the demand for miniature, electronic components and the development of high-density connectors. The consumer electronics industry has already implemented high-density connectors, while many avionics/military products still use traditional surface-mount and plated through-hole connectors. These traditional connectors are increasingly too large and cannot meet the signal capacity requirements of modern avionics/military product designs within the limited available printed circuit board space. In this study, two major types of high-density connectors, the fine-pitch leaded style and the area-array style, were installed on test boards using automated assembly with tin-lead and lead-free soldering processes. The assemblies were subjected to -55° to +125°C thermal cycle testing in accordance with IPC-9701, Performance Tests Methods and Qualification Requirements for Surface Mount Solder Attachments. The first part of this paper discusses results and observations from the new testing of fine-pitch style and area-array style connectors. The second part of this paper compares data for the fine-pitch connectors to previously tested area-array connectors. Tradeoffs between these two types of connectors, including producibility, reliability, printed circuit board space usage, rework, ease of assembly, and defect identification, are discussed. (Collins company white paper, October 2019)

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