by NILESH BADWE, KEVIN BYRD, OU JIN and PUBUDU GOONETILLEKE
Tin-bismuth (SnBi)-based low-temperature solders (LTS) can be used to create solder joints both when used in conjunction with an electronic package using tin-silver-copper (SAC) solder spheres or a SnBi-based solder sphere. In the case of a SAC-LTS solder joint, the resulting structure is referred to as “hybrid.” For an LTS-LTS solder joint, the structure is referred to as homogenous. Figure 1 illustrates the structure of each case.




A homogenous LTS solder joint can effectively eliminate a solder joint quality defect referred to as “hot tearing.” In a non-eutectic solder system, during cooling the solder will solidify over a range of temperatures. As the package returns to the room temperature shape, the dynamic warpage creates stress on the solder joints. If the solder joints are not fully solidified during this period, the joint can tear, which creates a crack-like signature post-SMT and may pose a risk to solder joint reliability. For a hybrid joint, this risk is increased by the lack of solder joint collapse during reflow. As the SAC solder ball does not fully melt, the unmelted portion of the joint acts as a standoff and prevents full collapse. Figure 4 shows the difference in post-reflow standoff height of a hybrid solder joint compared with a homogenous solder joint.
Details about hot tearing defects and process knobs to mitigate those in hybrid joints are discussed in a companion proceeding.5 The homogenous solder joint melts completely and creates a full collapse, which has been shown to help eliminate the occurrence of hot tearing (Figure 5) and provides a much wider process window.

Thermal cycle reliability: BGA assembly and testing details. To evaluate the thermal cycle fatigue performance of a hybrid joint vs. a homogenous joint, a 16.5mm x 28mm, 0.43mm pitch ball grid array (BGA) component was chosen as the test vehicle. The package used an electroless nickel-electroless palladium-immersion gold (ENEPIG) surface finish and a 250µm solder sphere. Half of the packages were built with a SAC 405 solder sphere, and the other half were built with a SnBi solder sphere with 40% Bi and supplier proprietary dopants. The packages were assembled on a 700µm thick, 15cm x 15cm printed circuit board with copper organic solderability preservative (Cu OSP) surface finish. Each test board had a single package placed at the center of the board. The test board was designed with a daisy chain to allow in-situ continuity monitoring during temperature cycle (TC) testing.
Boards were assembled using two different Sn-Bi LTS solder pastes. To accelerate fatigue failures and reduce testing time, a stencil was designed that did not print paste in certain known high-stress locations (Figure 6). Due to the depopulated stencil apertures, no solder joints were formed at those locations. The stress on the remaining joints were increased, thus reducing mean time to failure. A 100µm-thick nano-coated stencil was used with a 237.5µm round aperture for each pad. This resulted in a theoretical solder volume of 0.0046mm3. Compared to the 0.0086mm3 volume of the 254µm solder sphere, the resulting paste:ball volume ratio for the hybrid joints was 0.535, very close to the target 0.5 ratio (Table 1).

Test boards were thermal-cycled in an unloaded configuration using a -40º to 85ºC, 30 min. cycle. Electrical continuity was measured continuously in-situ. The sample size was nine boards per leg. Testing was continued until at least 80% of the boards had recorded a failure to permit a Weibull plot to be completed. Eight of nine packages were dyed and pulled post thermal cycling to identify crack type based on the failure interface as shown in Figure 3. The number of cracks larger than 80% of the solder joint area was measured for each crack type. One package from each leg was cross-sectioned to study the microstructure post thermal cycling.
Drop shock reliability: BGA assembly and testing details. A study was completed comparing the mechanical shock capability of a homogenous SAC interconnect, a hybrid SAC-LTS interconnect formed using paste volumes to result in optimum and extended Bi mixing, and a homogenous LTS interconnect. The daisy chain test vehicle was a 16.5mm x 28mm, 0.43mm pitch BGA. The package used an ENEPIG surface finish and a 250µm solder sphere. Half of the packages were built with a SAC 405 solder sphere, and the other half were built with a Sn-Bi solder sphere with 40% Bi and supplier proprietary dopants. For the hybrid and homogenous LTS solder joints, paste A was utilized. The homogenous SAC solder joints were formed using a SAC 305 solder paste. The BGA packages were soldered to a 700µm-thick, 30.5cm x 30.5cm test board. No corner adhesive was used. For this testing, the BGA joints were fully populated, as no-time-to-fail acceleration was required. The test board was designed with a daisy chain to permit solder joint electrical continuity to be continuously monitored in-situ during drop testing.
Mechanical drop testing was completed using a drop table and a variable acceleration (G) level, 2 ms pulse, ½ sine. The sample size was 10 boards per leg. For each sample, five drops were completed at a starting G level of 80G. If no electrical fails were recorded, the G level would be increased by 5G and five drops repeated. Testing continued until all samples had recorded an electrical fail. Capability is reported as ❮1% fail at 90% lower confidence limit (LCL).



For both pastes, the majority of failures for the homogenous solder joints was at the package (ENEPIG) interface, which is consistent with the expectation. Only paste B reflowed at 190°C, with LTS BGA showing a few failures at the PCB interface, as shown in Table 3. These cracks are fatigue-driven in the bulk solder (FIGURE 10). In the case of the hybrid solder joints, most of the failures were located at the PCB (OSP) interface, consistent with expectations. A smaller number of failures were noted at the package (ENEPIG) interface, however. As evident from the crack location variation, an inconsistent failure location results in a lower β parameter. To help with the argument, we define a crack location variability parameter (CLVP) as:
CLVP = minimum (No. of T2 cracks/No. of T3 cracks, No. of T3 cracks/No. of T2 cracks)
For hybrid joints in this study, no. of T3 cracks > no. of T2 cracks. Hence CLVP is T2/T3, whereas, for homogeneous LTS joints with predominant T2 failures, CLVP is T3/T2. This parameter captures the consistency of cracking locations for solder joints. As observed in Figure 9, it has an excellent correlation with Weibull β parameter. This further asserts variable cracking in a solder joint can impact thermal cycle life predictability.

Drop-shock testing results. All failures in the drop-shock reliability testing were at the package corner, unlike the thermal cycle testing. Failed samples from the drop-shock testing were submitted to a dye-and-pull process, and then crack type was documented. For the homogenous SAC samples, the primary failure location was cracking under the PCB pad into the board laminate (pad crater). Both hybrid sample legs cracked preferentially at the solder joint-PCB pad interface, indicating the hybrid SAC-LTS metallurgy is weaker than the ENEPIG-SAC interface. In the homogenous LTS samples, cracking occurred preferentially (>70% cracks) at the package side interface (T2 crack). SEM microstructure study confirmed the findings (FIGURE 11).

2. Hisaaki Takao, Akira Yamada and Hideo Hasegawa, “Mechanical Properties and Solder Joint Reliability of Low-Melting Sn-Bi-Cu Lead-Free Solder Alloy,” R&D Review of Toyota CRDL 39, no. 2, 2004.
3. Scott Mokler, Raiyo Aspandiar, Kevin Byrd, Olivia Chen, Satyajit Walwadkar, Kok Kwan Tang, Mukul Renavikar and Sandeep Sane, “The Application of Bi-based Solders for Low Temperature Reflow to Reduce Cost while Improving SMT Yields in Client Computing Systems,” SMTA International, September 2016.
4. Seiki Sakuyama, Toshiya Akamatsu, Keisuke Uenishi and Takehiko Sato, “Effects of a Third Element on Microstructure and Mechanical Properties of Eutectic Sn–Bi Solder,” Transactions of the Japan Institute of Electronics Packaging, vol. 2, no. 1, 2009.
5. Todd Harris, Kevin Byrd and Nilesh Badwe, “Root Cause and Solution to Mitigate the Hot Tear Defect Mode in Hybrid SAC-Low Temperature Solder Joints,” SMTA International, September 2019.
6. Satyajit Walwadkar, Suresh Guthikonda, Raiyo Aspandiar and George Hsieh, “A Novel Approach to Determine Mechanical Fatigue Performance of Solder Material using Single Solder Joint Test,” SMTA International, October 2018.
Ed.: This article was first published in the SMTA International Proceedings and is reprinted here with permission of the authors.
NILESH BADWE, KEVIN BYRD, OU JIN, PUBUDU GOONETILLEKE are with Intel (intel.com); nilesh.u.badwe@intel.com.