Demystifying Power Integrity
How to easily check current limits between a DC-DC converter and an FPGA.
by Ralf Brüning and Marcus Buecker
The design of power-supply structures on PCBs is not trivial. It requires careful consideration and techniques to achieve the best performance. Today’s high-pin-count devices need efficient power distribution systems permitting high-speed/high-frequency switching. The space available on PCBs is increasingly scarce. Thus, engineers fight for every square millimeter, using multiple layers for the layout of signal nets and power areas, parts of the power distribution which are then connected using dedicated power distribution network (PDN) via structures.

The narrowing of various supply voltages, coupled with increasing IC complexity and the number of voltage rails required, makes power integrity analysis inevitable for high-speed designs. This applies to AC as well as DC effects. The most compelling evidence is that modern circuits like (LP-)DDR memories operate at very low voltages (LP-DDR4 at 1.1V, for example).

Hence, typical power distribution systems today contain large numbers of vias connecting the different parts of the PDN across board layers. Often, large currents travel within these PDNs. Currents can reach dozens of amps when multiple FPGA signals are switching in parallel, while parasitic switching currents can reach even higher numbers for a very short period of time. Automatic via reinforcement functionalities within the PCB design environment often add fuel to the fire. This means automatically generated via structures may not be optimally designed against the required electrical power conditions imposed by increasing currents.

Temperature constrains current. The laws of physics dictate PCB traces and vias have a maximum current carrying capacity. A direct relationship exists between trace width/via dimensions and their current-carrying capacity. Specifically, any cross-sectional area of copper (trace width/thickness or via dimension) is a victim of temperature rise as a function of the current flow. This maximum allowed temperature typically constrains the maximum allowed current. PCB layout engineers often find this in the various IPC formulas dealing with PCB trace currents.1,2 Proper sizing and number of PDN vias for low resistance and long-term reliability are essential for successful PCB design.

This article describes how to easily check the current limit between a DC-DC converter and an FPGA, using the Zuken PI/EMI tool in a real-life example.

Figure 1. Investigated structure: the main power supply of an Intel Arria FPGA.
Simulation scenario. The supply system in our example is routed on two layers, connected by 68 power vias in total (FIGURE 1). The current limits can be checked directly using the DC analysis features of the analysis tool. An embedded DC solver is used to perform IR-drop analysis and quantify current distribution across the surface of the investigated power distribution system (FIGURE 3). The investigated case was simulated in less than 30 sec. (25µm discretization).

Such a fast simulation approach enables the execution of various parametric studies. These could be changing the PDN routing patterns or connection strategies or adding and deleting vias. Re-simulation cycles help elaborate the impact of such measures. Within the tool, users can manually create virtual via types to explore the solution space with respect to power flow and IR-drop.

In our example, closer studies reveal currents are not distributed equally between all vias of the power via array. For instance, a few vias carry the majority of the current, while most others show only smaller current values. We investigate this using the tabular view showing all via currents of the VCC system in the PI tool (FIGURE 4).

PDN vias between Layer-1 and Layer-4
Figure 2. PDN vias between Layer-1 and Layer-4.
DC analysis result (current distribution)
Figure 3. DC analysis result (current distribution).
Virtual PCN via with less DC resistance for what-if studies
Figure 4. Virtual PCN via with less DC resistance for what-if studies.
The via structures under investigation are identified by cross-probing between the PI/EMI analysis tool and the main PCB canvas in 2-D or 3-D. In this example, several of the vias carry only a minimal portion of the overall current, while others are overloaded. This situation may lead to wasted board space (unnecessary vias), while also running the risk of other vias overheating. Worst case: Vias could melt away over time during system operation.

Next, we use the integrated PI/EMI tool for analysis on potential design issues, such as the impact of adding or removing power vias. The maximum allowed current can be specified on a per-via basis to check for current-carrying violations.

Based on the initial results, various parametric studies have been performed in this case. In one instance, an additional PDN-via has been added and varied in its position in relation to coil L101. Furthermore, some of the vias considered unnecessary have been removed. The results of multiple DC simulation cycles have investigated the implications.

PDN via current results, original structure
Figure 5. PDN via current results, original structure.
PDN via current results, modified structure
Figure 6. PDN via current results, modified structure.
FIGURES 5 and 6 show the current distribution of the original structure compared to a via-array featuring that one additional via. Note the newly added via will now take most of the current (428mA).
PCB designers often struggle to find the optimal power/current carrying capability with a minimal number of vias, perhaps smaller vias. This is particularly true for small form-factors (e.g., IoT or medical applications) or complex high-speed designs. These can range from data center servers to industry automation or automotive ECUs and especially EV electronics. All these applications support various levels of high-current loads from the increasingly power-hungry MPUs, DSPs, FPGAs, or ASICs.

Designing power modules using modern DC/DC converters (and PMICs) requires advanced information on parasitic behavior of the copper spread over the board as part of the PDN. Easy-to-use and easy-to-access PI simulation techniques can be vital to enable proper PCB operation under such conditions.

  1. IPC-2152, “Standard for Determining Current Carrying Capacity in Printed Board Design,” August 2009.
  2. IPC-2221B, “Generic Standard on Printed Board Design,” November 2012.
Ralf Brüning is product manager and senior consultant for high-speed design systems at the Zuken EMC Technology Center in Paderborn, Germany, responsible for product marketing and business development for the Zuken SI, PI and EMC analysis tools; ralf.bruening@zuken.com. He will speak at the PCB West technical conference in October.