BGA Rules for Rigid-Flex PCBs
Strategies for vias and routing.
It seems every new design has at least one BGA component on the board. The 1.0mm pitch BGA has become vanilla. Even the 0.8mm pitch BGA is commonplace. These components are not limited to rigid PCBs; BGAs of all shapes and sizes are implemented in flex and rigid-flex designs as well.

The rules for BGAs are much the same whether the board is rigid or rigid-flex. Due to some of the material differences in a rigid-flex, however, extra care is recommended when it comes to the artwork and the trace routing in the BGA field.

Let’s start with pad and via design. For microvias, many suppliers recommend staying at or above 0.005″ diameter vias for reliability reasons. Much experience tells us vias smaller than 0.005″ tend to have a much lower mean time between failure (MTBF) than vias at or greater than 0.005″. In more benign applications, smaller vias may be an option. If the product will experience temperature extremes, however, the conservative bet is to stay above 0.005″ diameter microvias. Depending on the design and manufacturer, the associated pads may range from 0.010″ to 0.012″. Smaller pads risk a via sliding off the edge of the pad. If it does, the risk is the laser may cut through the dielectric and down to the next copper layer.

When using buried and through vias, manufacturers need more room to work on rigid-flex. Pad sizes for drilled vias are typically 0.012″ to 0.020″ larger, depending on laminating cycles, layer count and annular ring requirements. This is an area where consulting with your manufacturer early can be critical. Certain strategies can help reduce both the via and pad sizes. This will be key to routing the BGA.

Given the additional layer registration challenges on rigid-flex, fanouts and trace spacing can be more critical. As noted, 0.8mm and 1.0mm BGAs are well-established, and routing fanouts is straightforward. As we move to 0.65mm and smaller, down to 0.3mm, however, routing the artwork takes more care.

Things to consider:

  • Most fanout layers may be plated layers and thicker than the base copper; thus, resolving tight spaces is a bigger challenge.
  • Copper-filled vias and capped vias can drive extra copper plating, adding etch difficulty.
  • Staggered vias may permit thinner copper plating, making etching easier.
  • In some cases, reducing pad size and therefore annular ring may be preferred to gain spacing from pad to trace.
  • An inverted pyramid routing technique is often used for 0.5mm and smaller BGAs.
  • Routing traces between pads is rarely done for 0.4mm or smaller BGAs.

The smallest pitch/highest pin count BGA on a board will be the primary driver of the board construction. The 0.4mm and smaller BGAs eliminate many options, as the ways to design these are few. Essentially, the array pattern of the BGA will dictate the number of layers. No traces will run between pads. The inverted pyramid technique is used to work layer by layer and row by row to fan out all the BGA pads. For example, a 12 x 11 array 0.4mm BGA will require six layers to pin out every ball (FIGURE 1). There currently is no other way around this.

An inverted pyramid technique used to fan out BGA pads
Figure 1. An inverted pyramid technique used to fan out BGA pads.
Strangely, an area where designers get into trouble is when working with the larger BGA patterns. Because there is more room, it is more common to see traces routed between pads in the BGA field. This can be fine, provided attention is paid to details. Here are some situations where trouble can occur.

Traces are autorouted, and no extra work is done to truly center traces. The result is traces are often off-center, with minimum pad-to-trace spacing on one side and more spacing on the other. For example, you might see 0.0035″ space on one side and 0.0055″ on the other. If centered, we could have 0.0045″ on both sides. This is a huge improvement, making etching much easier overall. For every design, the tightest spacing on each layer will define how it gets etched.

An additional issue with lack of centering happens on external layers. Traces routed closer to pads on one side have a much higher risk of exposure by openings in the solder mask. This creates risk for an assembly short. Long story short, this is an unforced error that is easy to avoid with a little extra time at layout. It will be time well spent, resulting in higher yields and lower unit pricing over time.

Another issue arises when length-matching differential pairs. Often this can lead to routing serpentines within the BGA field. Keep the serpentine meandering outside the BGA pattern. This avoids tighter-than-needed spacing in an area where space already is at a premium. Also, it is normal to bring pairs into their pads, maintaining designed spacing as long as possible. This can cause one of the two traces in a pair to loop around a pad, rather than more efficiently route into its targeted pad, again consuming precious spacing.

Finally, there is the diagonal route through a BGA pattern. This creates many tight pad-to-trace intersections that could be avoided by finding another path. In general, the shortest path to reach a BGA pad is the best one.

In the end, we are looking for ways to optimize the design. With smaller and smaller BGA patterns, the challenges become more substantial for the designer. Thinking in microns or tenths of mils can make a difference. Optimizing artwork patterns and avoiding unnecessary difficult etch features can lead to a big payoff.

Nick Koop headshot
Nick Koop
is director of flex technology at TTM Technologies (, vice chairman of the IPC Flexible Circuits Committee and co-chair of the IPC-6013 Qualification and Performance Specification for Flexible Printed Boards Subcommittee; He and co-“Flexpert” Mark Finstad ( welcome your suggestions.