**PI**

DC vs. AC (aka static vs. transient). Historically, nearly all power conversations pertaining to printed circuit boards have been lumped into two categories, with the terms “power DC” and “power AC” emerging as almost standard terminology. Power DC is understandable as it addresses PDN capacity issues associated with inadequate copper.

Our experience with DC analysis reveals the simulation process, once thought to be complex, is nothing more than the visualization of Ohm’s law. With voltage defined in our DC supplies, and current by the operating requirements of each load, we found tools could readily calculate the resistance by extracting the geometry of the conductors. Using these resistance models in conjunction with the current needs of each IC (defined by their electrical specifications), it is easy to predict the DC voltage available in each chip given its distance from the source. This makes the cumulative resistance from the source the determining factor defining the DC performance each IC experienced.

The voltage loss observed during DC analysis is representative of the reductions expected when each device draws a continuous, unchanging current from its power source. This constant current, when drawn through the resistive network of our PCB, produces a voltage potential in the conductive path, reducing the realized value at the IC’s power pins. While this is infinitely valuable in establishing a base voltage, it does not completely define the true conditions. This is where power AC can help fill in gaps.

Adding time to the equation. Power AC is not intuitive; it’s not actually alternating current under investigation, but rather transient or changing current. While admittedly a much more accurate representation of the situation, it still obscures the true objective. Our goal is no variants at all: steady, unwavering power rails at each voltage, true to the defined level despite varying demand. Ideally, this should be the condition seen by every dependent IC regardless of the distance from the source or the demands of its neighbors.

To be concise, we want no AC, transients, spikes, droops, dips, or deviations, just rock-solid, steady voltage distribution networks capable of maintaining the voltage while responding to the instantaneous current demands of today’s high-speed devices. Power AC is all about eliminating voltage changes.

To fully validate the PDN we must look closer at the *actual* current present at the power pins of a load device. What we find is, while there is often a degree of continuous, steady current, there are also bursts of current at varying frequencies. These bursts are the subject of “transient power analysis,” often inaccurately referred to as “AC analysis.” With the new understanding that current can also vary over time and keeping our objective of “a steady minimum voltage at the load pins” in mind, we must reevaluate Ohm’s law.

Ohm’s law redux. We describe resistance using its complex definition: impedance. Impedance is simply the combination of resistance (R), which we know from DC analysis, and reactance. Reactance has both an inductive component, which resists changes in current, and a capacitive component, which resists changes in voltage. In combination, they don’t reduce the voltage available at the load pins as we saw with DC losses, but rather they act to restrict or impede the responsiveness to the burst demands we described (FIGURE 1). With the effects of reactance altering the timing as opposed to the amplitude of a power signal, we describe this behavior in terms of the effect on a sine wave, essentially advancing or retarding the signal and quantify it using degrees.

*actual*voltage at the load pins, we must account for losses from both resistance and reactance. Comprised of both an inductive and a capacitive component, both influenced by frequency, we soon find the reactance (and therefore the impedance) changes with the frequency. Initially, this might suggest we would need to determine frequency before the resultant reactance could be known. In practice, however, we approach this a bit differently. With voltage our primary concern, and knowing the loss of voltage results when the current (demanded by the load to operate) flows through the impedance of the PDN, it becomes clear that where impedance stays low, losses stay low. Therefore, our goal in PDN design is to maintain a low impedance over a range of frequencies, as opposed to just one. For example, maintaining an impedance at or below a specific goal (or “target”) for all frequencies between 1KHz and 1GHz will guarantee, via Ohm’s law, a voltage loss at or below an acceptable loss without concern for the frequency associated with the reactance (FIGURE 2).

Impedance. To some extent the terminology itself is confusing. Transient (AC) power analysis isn’t about simulating the time-dependent noise on the power plane at all. Instead, it’s about ensuring impedance is controlled. This way, any time-dependent variations in the current pass through a resistance so low it cannot produce a voltage high enough to be concerning. We control variation in the voltage by limiting resistance. Although each device has its own criteria for minimum voltage, as board designers, we determine how much variation we can permit in our supply voltage. Driven by the most demanding devices, acceptable “ripple,” or deviation from ideal voltage can be bounded simply by controlling the target impedance (FIGURE 3).