Routing
The Case for a 1.1mm BGA/CGA PACKAGE
A marginally larger package would cut design times and improve PCB yields and performance. by GERRY PARTIDA
Most electronics engineers know there is no 1.1mm BGA or CGA package. Because we are forced to use a 1mm pitch package, we live with tradeoffs. A slight increase in the pitch size, however, could satisfy the needs for today’s high I/O pin count designs.

This conclusion comes from my observations of building Class 3 and aerospace 1mm pitch products, and the challenges, setbacks, redesigns, returned product, and field failures we all endure.

Ideally, we would have the following allowances in a design for performance, layout, compliance and yield:

  • The ability to double tract conductors between via lands.
  • Conductors not less than 0.004″.
  • Spacing between conductors not less than 0.004″.
  • Drill-to-copper distance of 0.010″.
  • Drill diameters of 0.010″ and aspect ratios less than 12:1.
  • Annular ring that meets Class 3. (Design should have a land 0.014″ over the drill size.)
  • Meets copper plating in the hole 0.001″ minimum (IPC-6012 Class 3).
  • If via-in-pad, epoxy fill that meets IPC-6012.
  • A design that passes OM reflow (IPC-TM-650, method 2.6.8) and thermal shock (IPC-TM-650, method 2.6.27B) testing approaching 100%.
Currently the 1mm pitch does not permit this, and we enter a world of compromise and higher noncompliance results (FIGURE 1). Look at the tradeoffs in respect to IPC-6012 Class 3. Keep in mind for these complex builds with multiple lamination cycles, the loss of one panel can be $1,000 to $10,000 or more.

The issues for 1mm BGA pitch with dual traces include:

  • Class 3 annular ring requirement is relaxed to tangency or Class 2. This gains only 0.001″ additional space. Moreover, there is higher risk of breakout, nonconformance and rejection on an entire production panel.
  • Drill sizes are typically reduced to 0.0079″, gaining another 0.001″ of space. Aspect ratio can be 12:1 or higher for the same thickness. The customer may need to relax copper thickness requirements and change from long-established minimum copper requirements. A failed cross-section results in rejection of the entire production panel.
  • Dual conductors between via lands will have conductors that are 0.003″-0.0034″ in the BGA package. Conductor resistance becomes a concern. Fabricator yields for innerlayer processing drop.
  • Space for dual conductors limits differential pair and dielectric options. There is little room to change values or dielectric thickness. This reduces space, and also reduces innerlayer fabrication yields.
  • Drill to copper internal signal layers. The best scenario is drill to copper distance of 0.009″. I highly recommend 0.010″ or greater for reliability and field life. Here is the reason for a distance of 0.009″. Layer and drill registration will take up to 0.005″ of distance in a typical build. Dielectric removal (etchback, wicking, drill quality) typically will take 0.002″. IPC-6012 permits 0.00315 for Class 3, so with normal conditions we have used up 0.007″ of the 0.009″ spacing budget. Finally, IPC-2221 guidelines require 0.002″ minimum (worst-case condition) distance between 0V to 50V. We have now arrived at the value of 0.009″.
  • Drill-to-copper plane layer has the same distance rule, except the designer would like additional copper on the plane return for impedance. The impedance conductor edge is typically exactly over the plane clearance edge because they have the same exact design distance to the drill.
  • Via pad and epoxy filling a 0.0079″ drill bit might not meet the IPC-6012 60% fill requirement. The entire production panel could be rejected for a nonconformance condition.
  • OM testing failures can increase with the smaller diameter vias.
Image of 1mm pitch typical dual conductor
Figure 1. 1mm pitch typical dual conductor.
Image of Proposed 1.1mm pitch typical dual conductor
Figure 2. Proposed 1.1mm pitch typical dual conductor.
Here is conceptually how a 1.1mm pitch device provides a win-win for everyone in the supply chain:

  • The pitch is now 0.0433″.
  • The via land size is 0.0233″ with a 0.010″ drill.
    • The design annular ring is 0.0067″. Assured meeting tangency, best-in-class fabricators will meet Class 3.
    • Assuming PCB thickness is 0.100″, the aspect ratio is 10:1, which means no plating issues.
    • Can be epoxy-filled in compliance with the IPC-6012 60% fill requirement.
  • Dual conductors with 0.004″ lines and spaces.
    • Higher manufacturing yields.
    • Permits impedance line, space and dielectric flexibility.
  • Drill-to-copper for signal layers 0.0107″, assuming 0.0067″ annular ring and 0.004″ land-to-conductor space.
  • Drill-to-copper can be set to 0.010″ and permit “wider” copper return for impedance line. This adds 0.0007″, which is better than the current zero oversize for dual conductors on a 1mm pitch.

I can imagine the impact this size package could have on our industry. Many programs suffer and respin the design just to get to the point that fabricators reach yields in the 70% range. I have seen entire programs canceled. It seems we have been forced to use package sizes dictated by semiconductor providers that have never designed or fabricated a PCB. In researching this article, I read several semiconductor design guidelines for 1mm grid pitches. I thought I was reading fiction. One even recommended a drill-to-conductor space of 0.007″ for designers. Naturally, I hit the comment button and used words like “egregious.”

Let’s consider a different package size other than a whole number (1). We did it for 0.8mm, 0.65mm and other pitch sizes. I understand the package is bigger; for instance, a 40 x 40 1,600 I/O 1mm package grows from 1.575″ to 1.732″. But I have also seen there is generally enough room around these large packages and in almost all cases could accommodate the larger package.

The benefits of a 1.1mm grid package are many: faster design time, reduced cycle time, better signal performance, more current carrying capacity with a larger drill, compliant to IPC-6012 Class 3, higher PCB yields, and staying on schedule. If you believe this has merit and would like to enjoy the benefits, present this concept to your semiconductor suppliers.

Gerry Partida is director of technology at Summit Interconnect (summit-pcb.com); gerry.partida@summit-pcb.com.