Designer’s notebook
Microvias: An Answer to the High-Density Blues
Pros and cons – and costs.

It’s almost inevitable that a component that works well and lasts a long time will eventually be put on a list of parts not to be specified for mass production. Newer, better parts are on the way. The thinking goes that the microcontrollers and other devices on a board are already fine-pitch, so another one can be accommodated. That’s how we end up with those five-pin regulators with a tiny diamond-shaped pin trapped between four beveled rectangles.

Advantage: Component-to-component spacing. The via-in-pad trick enables high component density by enabling routing that is 100% internal to the board, with no exposed traces. The space normally set aside for the fan-out via can be used for the next component with the following stipulations:

  • Test access is maintained
  • Rework clearance (for desoldering)
  • Electrical isolation (shielding)
  • Thermal considerations (heat sink, heat pipe)
  • Mechanical interference (headroom)
  • Pick-and-place accuracy.

Within the above parameters, placement can be as tight as a jigsaw puzzle. Placement of discrete SMD components can get very cozy. When it comes to the smallest chip caps and resistors, a solder dam between their respective pads is sufficient space. This assumes the body of the part resides within the limits of the pads, as is typical of micro-caps. I normally recommend a solder mask dam with a minimum width of 100µm (4 mils). That said, 75µm is the new 100 as far as trends go among the fabricators putting down a solder dam.

An ancillary benefit of the via-in-pad method is shorter inductive loops of the decoupling capacitors as we skip the fan-out segments. Intuitively, the cap placement should create a bridge between a power pin and a local ground pin. In some applications, the exact pin-pair matters. Even if that information is in the relevant app notes, it is helpful to capture those types of provisions on the schematic diagram.

The most basic application of microvias. Setting the way-back machine to Y2K, the company I was working for was blazing a trail with a device package like a QFN (quad flat-pack no-lead), except it had two rings of pins around the central ground paddle instead of the usual one ring. They weren’t really pins either, more like bumps spaced at 0.5mm with square pads all around.

Figure 1. Many component types assume HDI technology will be used as a matter of course.

Figure 1. Many component types assume HDI technology will be used as a matter of course.

Figure 2. Microvias can be to get a good ground connection under hard-working parts.

Figure 2. Microvias can be to get a good ground connection under hard-working parts.

Figure 3. Microvias as a gateway to full HDI can be incorporated into EMI shields and QFP packages without compromising solderability.

Figure 3. Microvias as a gateway to full HDI can be incorporated into EMI shields and QFP packages without compromising solderability.

The only escape for that inner ring was to use laser technology to form the holes from the surface copper to the layer below. The hole can be as small as desired, but the need to plate the resulting hole is the limiting factor. What works best is a hole that is wider than it is deep. The width-to-depth aspect ratio is the key to reliable plating. We want a hole with more width than depth.

As an aside, technology roadmaps are pointing toward a 1:1 ratio somewhere in the future, but right now a 0.6:1 ratio is mainstream enough to use with confidence. Meanwhile, the size of the SMD pad for the device was 300µm, so that was the designated via size. The problem we’re trying to solve permits a finished hole size of 100µm when you allow for tolerance buildup.

Disadvantage: Locked into thin dielectric materials. The end result is the maximum dielectric thickness we could use is 60µm due to the aspect ratio mentioned above. Note the thin prepreg materials are always in demand for the sequential buildup process. Writing paper is around 100µm in thickness. This material is half that and integral to the whole HDI technology solution.

A four-layer board using microvias will have a thick middle layer between layers 2 and 3 to create sufficient backbone rigidity. This leaves an asymmetric Faraday cage where layer 2 routing is closer to layer 1 than to layer 3. The better impedance calculators will have an option for this type of innerlayer routing.

The downside is trace impedance is a function of dielectric thickness. A rule of thumb is a 50Ω line width correlates with the dielectric thickness. The trace width is about the same as the dielectric thickness. The dielectric constant, copper thickness and presence of solder mask all play a part in the actual impedance calculations. It would be an elite vendor that could produce line widths in this range, especially on the outer layers.

Getting away from those lossy 60µm lines can be achieved by creating voids in the layer immediately below the transmission line. Then, a top-layer trace would use layer 3 for a reference plane. Observing the not-unusual-for-analog idea of making the trace width match pad size, the reference plane can be as far down as you like. This advice is mainly about the type of trace you would only route on an outer layer in the first place. Designing RF amplifiers is a thing unto itself.

The microvia as a thermal path. One of the best uses of the microvia from the outer layer to the first innerlayer is in the middle of a QFP type of package where a big ground pin is in the center of the package. It doesn’t require much special handling to implement via-in-pad technology. The surface finish should be upgraded to electroless nickel/immersion gold (ENIG) to get flatter SMT pads that give better yields in assembly.

Adding vias to SMT pins should not alter the geometry of the original pin. Completely inside or outside of the pad rather than straddling the edge will make soldering more consistent. The fab notes should mention something about the maximum depth of dimples in the pad due to the via-in-pad. So-called “flat pad” technology might be a good keyword in your notes.

So, there you go. Microvias can tighten placement, shorten inductive loops, escape from “inescapable” pins and increase reliability of the overall assembly. The main cost is the materials that come with the technology. These benefits can be had on a board that requires only a single lamination cycle.

The other end of the price spectrum is a board composed completely of microvias. These boards have numerous lamination cycles, as all the layers are buildup layers. The construction will resemble that of substrates that go between the chip and board. They are common in phones, watches and assorted entertainment systems where they compete on size and performance. The more extreme systems add the complexity of flex circuits between different functional aspects of the design. When your board is using microvias to this extent, hats off to you! Meanwhile, getting started with the basics is easy.

John Burkhert Jr. headshot
John Burkhert Jr.
is a career PCB designer experienced in military, telecom, consumer hardware and, lately, the automotive industry. Originally, he was an RF specialist but is compelled to flip the bit now and then to fill the need for high-speed digital design. He enjoys playing bass and racing bikes when he’s not writing about or performing PCB layout. His column is produced by Cadence Design Systems and runs monthly.