Designer’s notebook
2 Approaches to Ensuring Even Copper Distribution
The best designs use the least amount of material possible.
Why evenly distribute copper on a PCB? Look at the material stackup as it alternates between conductor and dielectric material. The goal is to build a mirror image of copper weights as you work outward from the centerline.

Going beyond specifying alternating shape and route layers, the “greenest” PCB involves a minimum of etching. It’s intuitive that removing less material requires less time in the solvent tanks. Time is money, so that should be reason enough to have all layers biased toward copper fill.

Besides being easier on the equipment, copper-biased design will help maintain an even thickness across the entire board. While fabricators generally offer a +/-10% thickness tolerance, we often want a tighter distribution when it comes to the actual PCB thickness.

Basically, we must permit the 10% thickness tolerance, while aiming for a 5% variance by providing artwork that makes the most of the raw materials. The more evenly we design the board, the more consistent the outcome.

This applies to warpage (bow and twist) as a percentage of the overall length of the board. (As an aside, 0.75% is the new 1%, as we continue to push fabricators to deliver flatter boards that support high pin-count surface-mount devices.) The objective is printed circuit boards that are all the same thickness and flat as a pancake. (Mmm, pancakes!) The result we’re looking for is a high yield through assembly and a low defect rate down the road while saving resources during fabrication. OK, let’s do it.

HDI strategy. HDI offers quite a bit more latitude over traditional through-hole technology. My recommendation is to add a ground fill around the traces once the signal layers are fully connected. Once the copper flood is in place, it will be more obvious where a session of trace shoving will benefit the routing layers (FIGURE 1).

Chip
FIGURE 1. Isolating differential pairs and clocks (tinted yellow) is a good way to use copper flood on routing layers.
We’re looking to isolate differential pairs in their own Faraday cages. Clock nets and sense nets are also routed in their own channels for different reasons. Clocks are aggressors, while many sense lines are, you know, sensitive to outside influence, particularly from clocks and high-speed connections.

Once the traces are grouped to maximize copper flood while maintaining ideal inter-trace spacing, it will be relatively easy to stake out ground vias around the perimeter of the shapes on a layer-by-layer basis. The microvias used in HDI construction will fit into small spaces and will span only the layers necessary to stitch the local ground planes to the general ground planes on their dedicated layers.

HDI technology is always used for a reason. Invariably, one or more components is a technology driver, while other circuits on the board are overserved by such fine-pitch geometry. The microvias can still be useful as a via-in-pad solution for the larger power and ground pins on the typical voltage regulators, even though they were meant for more mainstream solutions.

Once microvias are in play, make the most of them. It is always much faster to make a microvia than a through-hole via. Yes, there are more of them as they sequence through the board one layer at a time, but the process is well understood and known to be fairly reliable.

Board with plated through-hole vias strategy. Budgetary constraints often compel us to keep the PCB construction low-tech. There are times when the old-school fabrication is all that is required, of course. The plated through-hole (PTH) process is the most reliable technique in use. We often find it under the hood of vehicles or onboard space rockets. No matter which end of the cost scale we consider, PTH boards have a long runway.

The thing is every via crosses every layer, so it’s easy to wind up with too much of a good thing when we attempt to use vias to create thermal paths or Faraday cages. The density of the stitching vias can create barriers on power and routing layers that diminish the flow.

In general, HDI boards are used to manage current density and high-speed transmission lines to a greater extent than their PTH cousins. In low-to-medium-density designs, the space between pins is more relaxed; thus, the routing solutions may be simpler.

We’ll still see a wide variance in metal loading between power, ground and signal layers (FIGURE 2). To prevent the PCB from resembling a potato chip, we want to even out the copper distribution. All the layers, no matter their function, should have a similar percentage of metallization coverage.

Metal loading
FIGURE 2. Metal loading in locations of too many vias would be disruptive.
You may be able to get there by flooding copper ground planes on all unused areas. The issue then becomes staking down the perimeter of each shape with vias. If they are left “floating,” then the shape is more likely to become a conduit for transferring noise from one place to another.

Ground bounce, ripple and other signal integrity effects are more common when the ground planes are not well connected wherever they go. Components, routing busses and power planes may make it difficult to add as many vias as necessary for each layer of copper pour.

For this reason, I tend to go for adding nonfunctional copper in places where ground pour is inadvisable. There can be a fabrication note that spells out the size, shape and spacing of the nonfunctional copper. Taping out an unbalanced board without a note on the subject will trigger the fab shop into asking permission to add “thieving.”

Fabricators are volunteering to do so to meet IPC requirements for flatness and thickness, but I’m sure they would be happier if you lead the way. I don’t want to leave it to them, so I create the thieving as part of the artwork, rather than relying on a fab note.

A final thought on implementing copper thieving. Ever heard of the golden ratio (FIGURE 3)? It’s something found in nature, like the chambers of a nautilus shell or a hurricane. It is also favored by architects and graphic designers. That is the geometry I like to use when creating an area of thieving. My favorite method is making rows of rectangles offset to resemble a brick wall, but a bunch of little dots will do as well for metal loading. I like to think the board gets a little more stiffness from the brick wall approach, although there is no proof of that.

Golden Ratio
FIGURE 3. The geometry of the golden ratio is seen in the small rectangle. Numerically, it is close to 1:1.6. (Source: Deposit Photos)
Spacing rules will drive the air gaps, and the size of the area to be filled will inform the size of the bricks. This filler method can be used on any layer but is most common on component and routing layers. Bottom line: Don’t wait to be asked to even the metal loading. Just go for it either by a design note or getting a little satisfaction with the layout tool.
John Burkhert Jr. headshot
John Burkhert Jr.
is a career PCB designer experienced in military, telecom, consumer hardware and, lately, the automotive industry. Originally, he was an RF specialist but is compelled to flip the bit now and then to fill the need for high-speed digital design. He enjoys playing bass and racing bikes when he’s not writing about or performing PCB layout. His column is produced by Cadence Design Systems and runs monthly.