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PDN Effectiveness: The Devil’s in the Decap Details
Understanding cap differences and modeling will help identify loop inductance issues early.

We’ve written for months about how to control power delivery. While we have learned the effects of layout on the PDN, we haven’t yet focused on the other major influencing factor: the decoupling capacitor.

These simple, 2-pin devices perform two main tasks: resist a change in voltage across their pins and accumulate and store “charge” that can be delivered from those pins to maintain that voltage. In the world of digital design, this “decoupling” function is huge and is arguably why we do power integrity (PI) simulation in the first place. The power demands of a product’s components are largely defined by its features and performance requirements, which determine supply sizes. Between those lies the power delivery network (PDN), a subject we’ve intensely studied. Composed almost entirely from capacitors and the copper that connects it all together, the success or failure of a PDN is often determined in layout. In previous articles, we’ve written about “loop inductance” and how it impacts the capacitors’ ability to do their job. A solid understanding of cap differences and modeling will help identify loop inductance issues early to ensure a successful PDN.

We are limiting this discussion to decoupling capacitors, also known as multilayer ceramic chip capacitors (MLCC), as these are the type seen in volume for most PCB tasks. While not minimizing the value of component engineering and other factors, we can generally determine the capacitor we need by considering the following parameters:

  • Size (0402, 0603)
  • Capacitance (10pF, 1pF)
  • Voltage (3V, 25V)
  • Tolerance (1%, 5%)
  • Temperature coefficient (TEMPCO: C0G, X5R).

For each parameter it is important to understand how your choices impact PDN, manufacturability, reliability, and sometimes overall design cost.

Size matters. The size of a capacitor is often the primary influence when selecting a component and can be varied to optimize the PDN. Smaller packages, such as 0201s, are desirable due to their low inductance but can be challenging to assemble. Larger packages, such as 0603s, take up valuable room on the PCB but may provide a lower mounting inductance by aligning with the breakout vias for a BGA. For a successful design, a balance needs to be achieved between inductance, capacity, manufacturability and cost.

Determining capacitance and voltage. Not a single reader will be surprised that capacitance and voltage are key considerations when choosing capacitors, as these values are based on the design requirements. While decoupling capacitance values can be calculated through complex design calculations, simulations or measurement results, many designers take a different approach. To produce a design that is both effective and responsive, select a capacitance value that provides the greatest amount of localized supplemental charge and replace some of the capacitors to obtain an acceptable frequency response (foreshadowing: the subject of next month’s article). Like most of the parts on a PCB, decoupling capacitors come with recommended operating conditions, including the acceptable input voltage. When deciding on the appropriate voltage, it’s not uncommon for designers to select a device based on a “derated” voltage. This is a reduction from the specified maximum voltage based on operating temperature and capacitor aging and will ensure functionality over the product lifespan.

Understanding tolerance across all operating conditions. Like any value in engineering, capacitance has tolerance. This is a range deemed close enough to the advertised value to be unnoticeable for the intended purpose. What’s often overlooked is tolerance only holds true for a specified temperature range. TEMPCO (aka “dielectric”) refers to the capacitor’s ability to remain within the tolerated capacitance value over the specified temperature range. Outside that range, the effective capacitance can drop off well beyond the specified tolerance. This is a vital parameter for decoupling capacitors, as the entire PDN’s ability to respond can be dramatically reduced to 50% when a board heats up or is exposed to wide environmental changes. TEMPCO is defined by a three-character sequence (letter, digit, letter) that refers to international standards that characterize temperature stability and are influenced by the insulating, or dielectric, material used to construct the capacitor (hence the misnomer). The capacitor cost significantly increases with stricter tolerances and wider operating temperature ranges; however, ignoring these aspects in your component selection can lead to field failure, especially in military and aerospace applications that experience extreme environmental conditions.

Figure 1. Typical part number “decoder.”
Figure 1. Typical part number “decoder.”

These five properties are so useful in differentiating capacitors, they often find their way into the vendor’s part numbering (FIGURE 1). For example, by looking at Kemet’s C0603C508K8GAC (0603 package) or AVX’s 08054W226MAT2A (4V) we can gather vital component information from just the part number. Many vendors value this inherent ease of use and provide guides to assist in the effort. These properties are only part of the equation, however.

Enter the capacitor model. While it is common for these properties to be used as the criteria to determine alternative components, they are not the only attributes to be considered. As demands on the PDN increase, and its margins and tolerances decrease, many designs are more sensitive to variability in the capacitor devices not captured by these properties alone. Understanding this, capacitor vendors have responded, providing Spice models and S-parameter models that include electrical aspects which can’t be characterized with simple attributes. Information beyond what a supplier could convey with properties alone can be contained in the model, including package inductance, internal resistance, and operating conditions such as temperature and bias voltage (FIGURE 2).

Figure 2. Beyond the ideal capacitor, Spice model syntax can include the package parasitic.
Figure 2. Beyond the ideal capacitor, Spice model syntax can include the package parasitic.

The Spice model for a capacitor is intended to provide an electrical view of the inner workings of the device, as seen from its external pins. It does this with a circuit approximation, composed of the basic RLC elements like how a circuit simulator would approximate a PCB wire as a transmission line. While this “inner view” of the capacitor can be useful to understand device behavior, when dealing with capacitors, we are most concerned with its behavior at the pins (as opposed to what’s going on inside). This is significant, particularly as an introduction to the other common modeling format, the network parameter, specifically an S-parameter.

The S-parameter opts to describe the capacitor behavior in terms of voltage and current from the outside at the device edge, treating the contents as a “black box.” While this makes the model useful, without any knowledge of its contents, it is necessary to know if the data within represent the device connected in series or in parallel. The capacitor separates the AC (or switching) parts of a signal from the DC (or level sensitive) part. During our board design, we may want to keep the DC and remove the AC, as in the case of a sensitive voltage source (i.e., filtering ripple noise from a voltage island). This requires a shunt configuration. Likewise, we may want to maintain the AC portion, removing the DC that requires a series configuration. This is common in a high-speed serial link where the DC part isn’t relative to the transmission but can cause a DC shift between driver and receiver.

Spice models and S-parameter models (FIGURE 3) can be incorporated into your simulations, are interchangeable and work in mixed combinations. Neither method is inherently more accurate, and vendors are free to choose one or both.

Figure 3. Spice and S-parameter models.
Figure 3. Spice and S-parameter models.

Building a complete model of your PDN. With the progression of solvers, simulators, and the readily available capacitor models, PDN creation and analysis are evolving. A basic understanding of capacitors is required to determine the necessary parameters for your design and incorporate realistic models into your simulation. By producing a complete and realistic picture of your power delivery network, analysis can be taken a step further, identifying loop inductance issues, optimizing capacitors, and ensuring target impedance.

Terry Jernberg Headshot
Terry Jernberg
is an applications engineer with EMA Design Automation (ema-eda.com), with a focus on PCB design and simulation. He spent his early career on signal integrity simulation for the defense industry and was fundamental in the adoption of these tools at EMC and Bose. A vocal advocate for simulation, his enthusiasm for physical modeling has expanded to include power and thermal capabilities.